779 lines
25 KiB
C
779 lines
25 KiB
C
/*
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* THE FOLLOWING FIRMWARE IS PROVIDED: (1) "AS IS" WITH NO WARRANTY; AND
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* (2)TO ENABLE ACCESS TO CODING INFORMATION TO GUIDE AND FACILITATE CUSTOMER.
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* CONSEQUENTLY, CMOSTEK SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR
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* CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT
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* OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION
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* CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
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*
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* Copyright (C) CMOSTEK SZ.
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*/
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/*!
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* @file cmt2300a.c
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* @brief CMT2300A transceiver RF chip driver
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*
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* @version 1.3
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* @date Jul 17 2017
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* @author CMOSTEK R@D
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*/
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#include "cmt2300a.h"
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/*! ********************************************************
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* @name CMT2300A_SoftReset
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* @desc Soft reset.
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* *********************************************************/
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void CMT2300A_SoftReset(void)
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{
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CMT2300A_WriteReg(0x7F, 0xFF);
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}
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/*! ********************************************************
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* @name CMT2300A_GetChipStatus
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* @desc Get the chip status.
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* @return
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* CMT2300A_STA_PUP
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* CMT2300A_STA_SLEEP
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* CMT2300A_STA_STBY
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* CMT2300A_STA_RFS
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* CMT2300A_STA_TFS
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* CMT2300A_STA_RX
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* CMT2300A_STA_TX
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* CMT2300A_STA_EEPROM
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* CMT2300A_STA_ERROR
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* CMT2300A_STA_CAL
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* *********************************************************/
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uint8_t CMT2300A_GetChipStatus(void)
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{
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return CMT2300A_ReadReg(CMT2300A_CUS_MODE_STA) & CMT2300A_MASK_CHIP_MODE_STA;
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}
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/*! ********************************************************
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* @name CMT2300A_AutoSwitchStatus
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* @desc Auto switch the chip status, and 10 ms as timeout.
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* @param nGoCmd: the chip next status
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* @return TRUE or FALSE
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* *********************************************************/
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bool CMT2300A_AutoSwitchStatus(uint8_t nGoCmd)
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{
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#ifdef ENABLE_AUTO_SWITCH_CHIP_STATUS
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uint32_t nBegTick = CMT2300A_GetTickCount();
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uint8_t nWaitStatus = 0;
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switch (nGoCmd) {
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case CMT2300A_GO_SLEEP:
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nWaitStatus = CMT2300A_STA_SLEEP;
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break;
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case CMT2300A_GO_STBY:
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nWaitStatus = CMT2300A_STA_STBY;
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break;
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case CMT2300A_GO_TFS:
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nWaitStatus = CMT2300A_STA_TFS;
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break;
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case CMT2300A_GO_TX:
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nWaitStatus = CMT2300A_STA_TX;
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break;
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case CMT2300A_GO_RFS:
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nWaitStatus = CMT2300A_STA_RFS;
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break;
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case CMT2300A_GO_RX:
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nWaitStatus = CMT2300A_STA_RX;
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break;
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}
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CMT2300A_WriteReg(CMT2300A_CUS_MODE_CTL, nGoCmd);
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while (CMT2300A_GetTickCount() - nBegTick < 10) {
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CMT2300A_DelayUs(100);
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if (nWaitStatus == CMT2300A_GetChipStatus())
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return true;
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if (CMT2300A_GO_TX == nGoCmd) {
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CMT2300A_DelayUs(100);
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if (CMT2300A_MASK_TX_DONE_FLG & CMT2300A_ReadReg(CMT2300A_CUS_INT_CLR1))
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return true;
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}
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if (CMT2300A_GO_RX == nGoCmd) {
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CMT2300A_DelayUs(100);
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if (CMT2300A_MASK_PKT_OK_FLG & CMT2300A_ReadReg(CMT2300A_CUS_INT_FLAG))
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return true;
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}
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}
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return false;
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#else
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CMT2300A_WriteReg(CMT2300A_CUS_MODE_CTL, nGoCmd);
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return true;
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#endif
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}
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/*! ********************************************************
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* @name CMT2300A_GoSleep
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* @desc Entry SLEEP mode.
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* @return TRUE or FALSE
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* *********************************************************/
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bool CMT2300A_GoSleep(void)
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{
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return CMT2300A_AutoSwitchStatus(CMT2300A_GO_SLEEP);
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}
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/*! ********************************************************
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* @name CMT2300A_GoStby
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* @desc Entry Sleep mode.
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* @return TRUE or FALSE
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* *********************************************************/
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bool CMT2300A_GoStby(void)
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{
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return CMT2300A_AutoSwitchStatus(CMT2300A_GO_STBY);
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}
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/*! ********************************************************
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* @name CMT2300A_GoTFS
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* @desc Entry TFS mode.
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* @return TRUE or FALSE
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* *********************************************************/
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bool CMT2300A_GoTFS(void)
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{
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return CMT2300A_AutoSwitchStatus(CMT2300A_GO_TFS);
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}
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/*! ********************************************************
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* @name CMT2300A_GoRFS
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* @desc Entry RFS mode.
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* @return TRUE or FALSE
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* *********************************************************/
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bool CMT2300A_GoRFS(void)
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{
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return CMT2300A_AutoSwitchStatus(CMT2300A_GO_RFS);
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}
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/*! ********************************************************
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* @name CMT2300A_GoTx
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* @desc Entry Tx mode.
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* @return TRUE or FALSE
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* *********************************************************/
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bool CMT2300A_GoTx(void)
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{
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return CMT2300A_AutoSwitchStatus(CMT2300A_GO_TX);
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}
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/*! ********************************************************
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* @name CMT2300A_GoRx
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* @desc Entry Rx mode.
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* @return TRUE or FALSE
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* *********************************************************/
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bool CMT2300A_GoRx(void)
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{
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return CMT2300A_AutoSwitchStatus(CMT2300A_GO_RX);
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}
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/*! ********************************************************
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* @name CMT2300A_ConfigGpio
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* @desc Config GPIO pins mode.
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* @param nGpioSel: GPIO1_SEL | GPIO2_SEL | GPIO3_SEL | GPIO4_SEL
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* GPIO1_SEL:
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* CMT2300A_GPIO1_SEL_DOUT/DIN
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* CMT2300A_GPIO1_SEL_INT1
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* CMT2300A_GPIO1_SEL_INT2
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* CMT2300A_GPIO1_SEL_DCLK
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*
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* GPIO2_SEL:
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* CMT2300A_GPIO2_SEL_INT1
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* CMT2300A_GPIO2_SEL_INT2
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* CMT2300A_GPIO2_SEL_DOUT/DIN
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* CMT2300A_GPIO2_SEL_DCLK
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*
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* GPIO3_SEL:
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* CMT2300A_GPIO3_SEL_CLKO
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* CMT2300A_GPIO3_SEL_DOUT/DIN
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* CMT2300A_GPIO3_SEL_INT2
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* CMT2300A_GPIO3_SEL_DCLK
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*
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* GPIO4_SEL:
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* CMT2300A_GPIO4_SEL_RSTIN
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* CMT2300A_GPIO4_SEL_INT1
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* CMT2300A_GPIO4_SEL_DOUT
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* CMT2300A_GPIO4_SEL_DCLK
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* *********************************************************/
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void CMT2300A_ConfigGpio(uint8_t nGpioSel)
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{
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CMT2300A_WriteReg(CMT2300A_CUS_IO_SEL, nGpioSel);
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}
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/*! ********************************************************
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* @name CMT2300A_ConfigInterrupt
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* @desc Config interrupt on INT1 and INT2.
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* @param nInt1Sel, nInt2Sel
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* CMT2300A_INT_SEL_RX_ACTIVE
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* CMT2300A_INT_SEL_TX_ACTIVE
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* CMT2300A_INT_SEL_RSSI_VLD
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* CMT2300A_INT_SEL_PREAM_OK
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* CMT2300A_INT_SEL_SYNC_OK
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* CMT2300A_INT_SEL_NODE_OK
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* CMT2300A_INT_SEL_CRC_OK
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* CMT2300A_INT_SEL_PKT_OK
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* CMT2300A_INT_SEL_SL_TMO
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* CMT2300A_INT_SEL_RX_TMO
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* CMT2300A_INT_SEL_TX_DONE
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* CMT2300A_INT_SEL_RX_FIFO_NMTY
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* CMT2300A_INT_SEL_RX_FIFO_TH
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* CMT2300A_INT_SEL_RX_FIFO_FULL
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* CMT2300A_INT_SEL_RX_FIFO_WBYTE
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* CMT2300A_INT_SEL_RX_FIFO_OVF
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* CMT2300A_INT_SEL_TX_FIFO_NMTY
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* CMT2300A_INT_SEL_TX_FIFO_TH
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* CMT2300A_INT_SEL_TX_FIFO_FULL
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* CMT2300A_INT_SEL_STATE_IS_STBY
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* CMT2300A_INT_SEL_STATE_IS_FS
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* CMT2300A_INT_SEL_STATE_IS_RX
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* CMT2300A_INT_SEL_STATE_IS_TX
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* CMT2300A_INT_SEL_LED
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* CMT2300A_INT_SEL_TRX_ACTIVE
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* CMT2300A_INT_SEL_PKT_DONE
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* *********************************************************/
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void CMT2300A_ConfigInterrupt(uint8_t nInt1Sel, uint8_t nInt2Sel)
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{
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nInt1Sel &= CMT2300A_MASK_INT1_SEL;
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nInt1Sel |= (~CMT2300A_MASK_INT1_SEL) & CMT2300A_ReadReg(CMT2300A_CUS_INT1_CTL);
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CMT2300A_WriteReg(CMT2300A_CUS_INT1_CTL, nInt1Sel);
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nInt2Sel &= CMT2300A_MASK_INT2_SEL;
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nInt2Sel |= (~CMT2300A_MASK_INT2_SEL) & CMT2300A_ReadReg(CMT2300A_CUS_INT2_CTL);
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CMT2300A_WriteReg(CMT2300A_CUS_INT2_CTL, nInt2Sel);
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}
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/*! ********************************************************
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* @name CMT2300A_SetInterruptPolar
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* @desc Set the polarity of the interrupt.
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* @param bEnable(TRUE): active-high (default)
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* bEnable(FALSE): active-low
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* *********************************************************/
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void CMT2300A_SetInterruptPolar(bool bActiveHigh)
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{
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uint8_t tmp = CMT2300A_ReadReg(CMT2300A_CUS_INT1_CTL);
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if (bActiveHigh)
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tmp &= ~CMT2300A_MASK_INT_POLAR;
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else
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tmp |= CMT2300A_MASK_INT_POLAR;
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CMT2300A_WriteReg(CMT2300A_CUS_INT1_CTL, tmp);
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}
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/*! ********************************************************
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* @name CMT2300A_SetFifoThreshold
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* @desc Set FIFO threshold.
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* @param nFifoThreshold
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* *********************************************************/
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void CMT2300A_SetFifoThreshold(uint8_t nFifoThreshold)
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{
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uint8_t tmp = CMT2300A_ReadReg(CMT2300A_CUS_PKT29);
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tmp &= ~CMT2300A_MASK_FIFO_TH;
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tmp |= nFifoThreshold & CMT2300A_MASK_FIFO_TH;
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CMT2300A_WriteReg(CMT2300A_CUS_PKT29, tmp);
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}
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/*! ********************************************************
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* @name CMT2300A_EnableAntennaSwitch
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* @desc Enable antenna switch, output TX_ACTIVE/RX_ACTIVE
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* via GPIO1/GPIO2.
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* @param nMode
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* 0: RF_SWT1_EN=1, RF_SWT2_EN=0
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* GPIO1: RX_ACTIVE, GPIO2: TX_ACTIVE
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* 1: RF_SWT1_EN=0, RF_SWT2_EN=1
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* GPIO1: RX_ACTIVE, GPIO2: ~RX_ACTIVE
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* *********************************************************/
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void CMT2300A_EnableAntennaSwitch(uint8_t nMode)
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{
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uint8_t tmp = CMT2300A_ReadReg(CMT2300A_CUS_INT1_CTL);
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if (0 == nMode) {
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tmp |= CMT2300A_MASK_RF_SWT1_EN;
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tmp &= ~CMT2300A_MASK_RF_SWT2_EN;
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} else if (1 == nMode) {
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tmp &= ~CMT2300A_MASK_RF_SWT1_EN;
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tmp |= CMT2300A_MASK_RF_SWT2_EN;
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}
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CMT2300A_WriteReg(CMT2300A_CUS_INT1_CTL, tmp);
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}
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/*! ********************************************************
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* @name CMT2300A_EnableInterrupt
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* @desc Enable interrupt.
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* @param nEnable
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* CMT2300A_MASK_SL_TMO_EN |
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* CMT2300A_MASK_RX_TMO_EN |
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* CMT2300A_MASK_TX_DONE_EN |
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* CMT2300A_MASK_PREAM_OK_EN |
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* CMT2300A_MASK_SYNC_OK_EN |
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* CMT2300A_MASK_NODE_OK_EN |
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* CMT2300A_MASK_CRC_OK_EN |
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* CMT2300A_MASK_PKT_DONE_EN
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* *********************************************************/
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void CMT2300A_EnableInterrupt(uint8_t nEnable)
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{
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CMT2300A_WriteReg(CMT2300A_CUS_INT_EN, nEnable);
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}
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/*! ********************************************************
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* @name CMT2300A_EnableRxFifoAutoClear
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* @desc Auto clear Rx FIFO before entry Rx mode.
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* @param bEnable(TRUE): Enable it(default)
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* bEnable(FALSE): Disable it
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* *********************************************************/
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void CMT2300A_EnableRxFifoAutoClear(bool bEnable)
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{
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uint8_t tmp = CMT2300A_ReadReg(CMT2300A_CUS_FIFO_CTL);
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if (bEnable)
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tmp &= ~CMT2300A_MASK_FIFO_AUTO_CLR_DIS;
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else
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tmp |= CMT2300A_MASK_FIFO_AUTO_CLR_DIS;
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CMT2300A_WriteReg(CMT2300A_CUS_FIFO_CTL, tmp);
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}
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/*! ********************************************************
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* @name CMT2300A_EnableFifoMerge
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* @desc Enable FIFO merge.
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* @param bEnable(TRUE): use a single 64-byte FIFO for either Tx or Rx
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* bEnable(FALSE): use a 32-byte FIFO for Tx and another 32-byte FIFO for Rx(default)
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* *********************************************************/
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void CMT2300A_EnableFifoMerge(bool bEnable)
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{
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uint8_t tmp = CMT2300A_ReadReg(CMT2300A_CUS_FIFO_CTL);
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if (bEnable)
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tmp |= CMT2300A_MASK_FIFO_MERGE_EN;
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else
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tmp &= ~CMT2300A_MASK_FIFO_MERGE_EN;
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CMT2300A_WriteReg(CMT2300A_CUS_FIFO_CTL, tmp);
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}
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/*! ********************************************************
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* @name CMT2300A_EnableReadFifo
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* @desc Enable SPI to read the FIFO.
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* *********************************************************/
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void CMT2300A_EnableReadFifo(void)
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{
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uint8_t tmp = CMT2300A_ReadReg(CMT2300A_CUS_FIFO_CTL);
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tmp &= ~CMT2300A_MASK_SPI_FIFO_RD_WR_SEL;
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tmp &= ~CMT2300A_MASK_FIFO_RX_TX_SEL;
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CMT2300A_WriteReg(CMT2300A_CUS_FIFO_CTL, tmp);
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}
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/*! ********************************************************
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* @name CMT2300A_EnableWriteFifo
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* @desc Enable SPI to write the FIFO.
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* *********************************************************/
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void CMT2300A_EnableWriteFifo(void)
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{
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uint8_t tmp = CMT2300A_ReadReg(CMT2300A_CUS_FIFO_CTL);
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tmp |= CMT2300A_MASK_SPI_FIFO_RD_WR_SEL;
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tmp |= CMT2300A_MASK_FIFO_RX_TX_SEL;
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CMT2300A_WriteReg(CMT2300A_CUS_FIFO_CTL, tmp);
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}
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/*! ********************************************************
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* @name CMT2300A_RestoreFifo
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* @desc Restore the FIFO.
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* *********************************************************/
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void CMT2300A_RestoreFifo(void)
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{
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CMT2300A_WriteReg(CMT2300A_CUS_FIFO_CLR, CMT2300A_MASK_FIFO_RESTORE);
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}
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/*! ********************************************************
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* @name CMT2300A_ClearFifo
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* @desc Clear the Tx FIFO.
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* @return FIFO flags
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* CMT2300A_MASK_RX_FIFO_FULL_FLG |
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* CMT2300A_MASK_RX_FIFO_NMTY_FLG |
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* CMT2300A_MASK_RX_FIFO_TH_FLG |
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* CMT2300A_MASK_RX_FIFO_OVF_FLG |
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* CMT2300A_MASK_TX_FIFO_FULL_FLG |
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* CMT2300A_MASK_TX_FIFO_NMTY_FLG |
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* CMT2300A_MASK_TX_FIFO_TH_FLG
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* *********************************************************/
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uint8_t CMT2300A_ClearTxFifo(void)
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{
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uint8_t tmp = CMT2300A_ReadReg(CMT2300A_CUS_FIFO_FLAG);
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CMT2300A_WriteReg(CMT2300A_CUS_FIFO_CLR, CMT2300A_MASK_FIFO_CLR_TX);
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return tmp;
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}
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/*! ********************************************************
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* @name CMT2300A_ClearFifo
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* @desc Clear the Rx FIFO.
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* @return FIFO flags
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* CMT2300A_MASK_RX_FIFO_FULL_FLG |
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* CMT2300A_MASK_RX_FIFO_NMTY_FLG |
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* CMT2300A_MASK_RX_FIFO_TH_FLG |
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* CMT2300A_MASK_RX_FIFO_OVF_FLG |
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* CMT2300A_MASK_TX_FIFO_FULL_FLG |
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* CMT2300A_MASK_TX_FIFO_NMTY_FLG |
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* CMT2300A_MASK_TX_FIFO_TH_FLG
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* *********************************************************/
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uint8_t CMT2300A_ClearRxFifo(void)
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{
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uint8_t tmp = CMT2300A_ReadReg(CMT2300A_CUS_FIFO_FLAG);
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CMT2300A_WriteReg(CMT2300A_CUS_FIFO_CLR, CMT2300A_MASK_FIFO_CLR_RX);
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return tmp;
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}
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/*! ********************************************************
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* @name CMT2300A_ClearInterruptFlags
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* @desc Clear all interrupt flags.
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* @return Some interrupt flags
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* CMT2300A_MASK_SL_TMO_EN |
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* CMT2300A_MASK_RX_TMO_EN |
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* CMT2300A_MASK_TX_DONE_EN |
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* CMT2300A_MASK_PREAM_OK_FLG |
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* CMT2300A_MASK_SYNC_OK_FLG |
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* CMT2300A_MASK_NODE_OK_FLG |
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* CMT2300A_MASK_CRC_OK_FLG |
|
|
* CMT2300A_MASK_PKT_OK_FLG
|
|
* *********************************************************/
|
|
uint8_t CMT2300A_ClearInterruptFlags(void)
|
|
{
|
|
uint8_t nFlag1, nFlag2;
|
|
uint8_t nClr1 = 0;
|
|
uint8_t nClr2 = 0;
|
|
uint8_t nRet = 0;
|
|
uint8_t nIntPolar;
|
|
|
|
nIntPolar = CMT2300A_ReadReg(CMT2300A_CUS_INT1_CTL);
|
|
nIntPolar = (nIntPolar & CMT2300A_MASK_INT_POLAR) ? 1 : 0;
|
|
|
|
nFlag1 = CMT2300A_ReadReg(CMT2300A_CUS_INT_FLAG);
|
|
nFlag2 = CMT2300A_ReadReg(CMT2300A_CUS_INT_CLR1);
|
|
|
|
if (nIntPolar) {
|
|
/* Interrupt flag active-low */
|
|
nFlag1 = ~nFlag1;
|
|
nFlag2 = ~nFlag2;
|
|
}
|
|
|
|
if (CMT2300A_MASK_LBD_FLG & nFlag1) {
|
|
nClr2 |= CMT2300A_MASK_LBD_CLR; /* Clear LBD_FLG */
|
|
}
|
|
|
|
if (CMT2300A_MASK_COL_ERR_FLG & nFlag1) {
|
|
nClr2 |= CMT2300A_MASK_PKT_DONE_CLR; /* Clear COL_ERR_FLG by PKT_DONE_CLR */
|
|
}
|
|
|
|
if (CMT2300A_MASK_PKT_ERR_FLG & nFlag1) {
|
|
nClr2 |= CMT2300A_MASK_PKT_DONE_CLR; /* Clear PKT_ERR_FLG by PKT_DONE_CLR */
|
|
}
|
|
|
|
if (CMT2300A_MASK_PREAM_OK_FLG & nFlag1) {
|
|
nClr2 |= CMT2300A_MASK_PREAM_OK_CLR; /* Clear PREAM_OK_FLG */
|
|
nRet |= CMT2300A_MASK_PREAM_OK_FLG; /* Return PREAM_OK_FLG */
|
|
}
|
|
|
|
if (CMT2300A_MASK_SYNC_OK_FLG & nFlag1) {
|
|
nClr2 |= CMT2300A_MASK_SYNC_OK_CLR; /* Clear SYNC_OK_FLG */
|
|
nRet |= CMT2300A_MASK_SYNC_OK_FLG; /* Return SYNC_OK_FLG */
|
|
}
|
|
|
|
if (CMT2300A_MASK_NODE_OK_FLG & nFlag1) {
|
|
nClr2 |= CMT2300A_MASK_NODE_OK_CLR; /* Clear NODE_OK_FLG */
|
|
nRet |= CMT2300A_MASK_NODE_OK_FLG; /* Return NODE_OK_FLG */
|
|
}
|
|
|
|
if (CMT2300A_MASK_CRC_OK_FLG & nFlag1) {
|
|
nClr2 |= CMT2300A_MASK_CRC_OK_CLR; /* Clear CRC_OK_FLG */
|
|
nRet |= CMT2300A_MASK_CRC_OK_FLG; /* Return CRC_OK_FLG */
|
|
}
|
|
|
|
if (CMT2300A_MASK_PKT_OK_FLG & nFlag1) {
|
|
nClr2 |= CMT2300A_MASK_PKT_DONE_CLR; /* Clear PKT_OK_FLG */
|
|
nRet |= CMT2300A_MASK_PKT_OK_FLG; /* Return PKT_OK_FLG */
|
|
}
|
|
|
|
if (CMT2300A_MASK_SL_TMO_FLG & nFlag2) {
|
|
nClr1 |= CMT2300A_MASK_SL_TMO_CLR; /* Clear SL_TMO_FLG */
|
|
nRet |= CMT2300A_MASK_SL_TMO_EN; /* Return SL_TMO_FLG by SL_TMO_EN */
|
|
}
|
|
|
|
if (CMT2300A_MASK_RX_TMO_FLG & nFlag2) {
|
|
nClr1 |= CMT2300A_MASK_RX_TMO_CLR; /* Clear RX_TMO_FLG */
|
|
nRet |= CMT2300A_MASK_RX_TMO_EN; /* Return RX_TMO_FLG by RX_TMO_EN */
|
|
}
|
|
|
|
if (CMT2300A_MASK_TX_DONE_FLG & nFlag2) {
|
|
nClr1 |= CMT2300A_MASK_TX_DONE_CLR; /* Clear TX_DONE_FLG */
|
|
nRet |= CMT2300A_MASK_TX_DONE_EN; /* Return TX_DONE_FLG by TX_DONE_EN */
|
|
}
|
|
|
|
CMT2300A_WriteReg(CMT2300A_CUS_INT_CLR1, nClr1);
|
|
CMT2300A_WriteReg(CMT2300A_CUS_INT_CLR2, nClr2);
|
|
|
|
if (nIntPolar) {
|
|
/* Interrupt flag active-low */
|
|
nRet = ~nRet;
|
|
}
|
|
|
|
return nRet;
|
|
}
|
|
|
|
/*! ********************************************************
|
|
* @name CMT2300A_ConfigTxDin
|
|
* @desc Used to select whether to use GPIO1 or GPIO2 or GPIO3
|
|
* as DIN in the direct mode. It only takes effect when
|
|
* call CMT2300A_EnableTxDin(TRUE) in the direct mode.
|
|
* @param nDinSel
|
|
* CMT2300A_TX_DIN_SEL_GPIO1
|
|
* CMT2300A_TX_DIN_SEL_GPIO2
|
|
* CMT2300A_TX_DIN_SEL_GPIO3
|
|
* *********************************************************/
|
|
void CMT2300A_ConfigTxDin(uint8_t nDinSel)
|
|
{
|
|
uint8_t tmp = CMT2300A_ReadReg(CMT2300A_CUS_FIFO_CTL);
|
|
tmp &= ~CMT2300A_MASK_TX_DIN_SEL;
|
|
tmp |= nDinSel;
|
|
CMT2300A_WriteReg(CMT2300A_CUS_FIFO_CTL, tmp);
|
|
}
|
|
|
|
/*! ********************************************************
|
|
* @name CMT2300A_EnableTxDin
|
|
* @desc Used to change GPIO1/GPIO2/GPIO3 between DOUT and DIN.
|
|
* @param bEnable(TRUE): used as DIN
|
|
* bEnable(FALSE): used as DOUT(default)
|
|
* *********************************************************/
|
|
void CMT2300A_EnableTxDin(bool bEnable)
|
|
{
|
|
uint8_t tmp = CMT2300A_ReadReg(CMT2300A_CUS_FIFO_CTL);
|
|
|
|
if (bEnable)
|
|
tmp |= CMT2300A_MASK_TX_DIN_EN;
|
|
else
|
|
tmp &= ~CMT2300A_MASK_TX_DIN_EN;
|
|
|
|
CMT2300A_WriteReg(CMT2300A_CUS_FIFO_CTL, tmp);
|
|
}
|
|
|
|
/*! ********************************************************
|
|
* @name CMT2300A_EnableTxDinInvert
|
|
* @desc Used to invert DIN data in direct mode.
|
|
* @param bEnable(TRUE): invert DIN
|
|
* bEnable(FALSE): not invert DIN(default)
|
|
* *********************************************************/
|
|
void CMT2300A_EnableTxDinInvert(bool bEnable)
|
|
{
|
|
uint8_t tmp = CMT2300A_ReadReg(CMT2300A_CUS_INT2_CTL);
|
|
|
|
if (bEnable)
|
|
tmp |= CMT2300A_MASK_TX_DIN_INV;
|
|
else
|
|
tmp &= ~CMT2300A_MASK_TX_DIN_INV;
|
|
|
|
CMT2300A_WriteReg(CMT2300A_CUS_INT2_CTL, tmp);
|
|
}
|
|
|
|
/*! ********************************************************
|
|
* @name CMT2300A_IsExist
|
|
* @desc Chip indentify.
|
|
* @return TRUE: chip is exist, FALSE: chip not found
|
|
* *********************************************************/
|
|
bool CMT2300A_IsExist(void)
|
|
{
|
|
uint8_t back, dat;
|
|
|
|
back = CMT2300A_ReadReg(CMT2300A_CUS_PKT17);
|
|
CMT2300A_WriteReg(CMT2300A_CUS_PKT17, 0xAA);
|
|
|
|
dat = CMT2300A_ReadReg(CMT2300A_CUS_PKT17);
|
|
CMT2300A_WriteReg(CMT2300A_CUS_PKT17, back);
|
|
|
|
if (0xAA == dat)
|
|
return true;
|
|
else
|
|
return false;
|
|
}
|
|
|
|
/*! ********************************************************
|
|
* @name CMT2300A_GetRssiCode
|
|
* @desc Get RSSI code.
|
|
* @return RSSI code
|
|
* *********************************************************/
|
|
uint8_t CMT2300A_GetRssiCode(void)
|
|
{
|
|
return CMT2300A_ReadReg(CMT2300A_CUS_RSSI_CODE);
|
|
}
|
|
|
|
/*! ********************************************************
|
|
* @name CMT2300A_GetRssiDBm
|
|
* @desc Get RSSI dBm.
|
|
* @return dBm
|
|
* *********************************************************/
|
|
int CMT2300A_GetRssiDBm(void)
|
|
{
|
|
return (int)CMT2300A_ReadReg(CMT2300A_CUS_RSSI_DBM) - 128;
|
|
}
|
|
|
|
/*! ********************************************************
|
|
* @name CMT2300A_SetFrequencyChannel
|
|
* @desc This defines up to 255 frequency channel
|
|
* for fast frequency hopping operation.
|
|
* @param nChann: the frequency channel
|
|
* *********************************************************/
|
|
void CMT2300A_SetFrequencyChannel(const uint8_t nChann)
|
|
{
|
|
CMT2300A_WriteReg(CMT2300A_CUS_FREQ_CHNL, nChann);
|
|
}
|
|
|
|
/*! ********************************************************
|
|
* @name CMT2300A_SetFrequencyStep
|
|
* @desc This defines the frequency channel step size
|
|
* for fast frequency hopping operation.
|
|
* One step size is 2.5 kHz.
|
|
* @param nOffset: the frequency step
|
|
* *********************************************************/
|
|
void CMT2300A_SetFrequencyStep(uint8_t nOffset)
|
|
{
|
|
CMT2300A_WriteReg(CMT2300A_CUS_FREQ_OFS, nOffset);
|
|
}
|
|
|
|
/*! ********************************************************
|
|
* @name CMT2300A_SetPayloadLength
|
|
* @desc Set payload length.
|
|
* @param nLength
|
|
* *********************************************************/
|
|
void CMT2300A_SetPayloadLength(uint16_t nLength)
|
|
{
|
|
uint8_t tmp = CMT2300A_ReadReg(CMT2300A_CUS_PKT14);
|
|
|
|
tmp &= ~CMT2300A_MASK_PAYLOAD_LENG_10_8;
|
|
tmp |= (nLength >> 4) & CMT2300A_MASK_PAYLOAD_LENG_10_8;
|
|
CMT2300A_WriteReg(CMT2300A_CUS_PKT14, tmp);
|
|
|
|
tmp = nLength & CMT2300A_MASK_PAYLOAD_LENG_7_0;
|
|
CMT2300A_WriteReg(CMT2300A_CUS_PKT15, tmp);
|
|
}
|
|
|
|
/*! ********************************************************
|
|
* @name CMT2300A_EnableLfosc
|
|
* @desc If you need use sleep timer, you should enable LFOSC.
|
|
* @param bEnable(TRUE): Enable it(default)
|
|
* bEnable(FALSE): Disable it
|
|
* *********************************************************/
|
|
void CMT2300A_EnableLfosc(bool bEnable)
|
|
{
|
|
uint8_t tmp = CMT2300A_ReadReg(CMT2300A_CUS_SYS2);
|
|
|
|
if (bEnable) {
|
|
tmp |= CMT2300A_MASK_LFOSC_RECAL_EN;
|
|
tmp |= CMT2300A_MASK_LFOSC_CAL1_EN;
|
|
tmp |= CMT2300A_MASK_LFOSC_CAL2_EN;
|
|
} else {
|
|
tmp &= ~CMT2300A_MASK_LFOSC_RECAL_EN;
|
|
tmp &= ~CMT2300A_MASK_LFOSC_CAL1_EN;
|
|
tmp &= ~CMT2300A_MASK_LFOSC_CAL2_EN;
|
|
}
|
|
|
|
CMT2300A_WriteReg(CMT2300A_CUS_SYS2, tmp);
|
|
}
|
|
|
|
/*! ********************************************************
|
|
* @name CMT2300A_EnableLfoscOutput
|
|
* @desc LFOSC clock is output via GPIO3.
|
|
* @param bEnable(TRUE): Enable it
|
|
* bEnable(FALSE): Disable it(default)
|
|
* *********************************************************/
|
|
void CMT2300A_EnableLfoscOutput(bool bEnable)
|
|
{
|
|
uint8_t tmp = CMT2300A_ReadReg(CMT2300A_CUS_INT2_CTL);
|
|
|
|
if (bEnable)
|
|
tmp |= CMT2300A_MASK_LFOSC_OUT_EN;
|
|
else
|
|
tmp &= ~CMT2300A_MASK_LFOSC_OUT_EN;
|
|
|
|
CMT2300A_WriteReg(CMT2300A_CUS_INT2_CTL, tmp);
|
|
}
|
|
|
|
/*! ********************************************************
|
|
* @name CMT2300A_EnableAfc
|
|
* @desc AFC enable or disanble.
|
|
* @param bEnable(TRUE): Enable it
|
|
* bEnable(FALSE): Disable it(default)
|
|
* *********************************************************/
|
|
void CMT2300A_EnableAfc(bool bEnable)
|
|
{
|
|
uint8_t tmp = CMT2300A_ReadReg(CMT2300A_CUS_FSK5);
|
|
|
|
if (bEnable)
|
|
tmp |= 0x10;
|
|
else
|
|
tmp &= ~0x10;
|
|
|
|
CMT2300A_WriteReg(CMT2300A_CUS_FSK5, tmp);
|
|
}
|
|
|
|
/*! ********************************************************
|
|
* @name CMT2300A_SetAfcOvfTh
|
|
* @desc This is optional, only needed when using Rx fast frequency hopping.
|
|
* @param afcOvfTh: AFC_OVF_TH see AN142 and AN197 for details.
|
|
* *********************************************************/
|
|
void CMT2300A_SetAfcOvfTh(uint8_t afcOvfTh)
|
|
{
|
|
CMT2300A_WriteReg(CMT2300A_CUS_FSK4, afcOvfTh);
|
|
}
|
|
|
|
/*! ********************************************************
|
|
* @name CMT2300A_Init
|
|
* @desc Initialize chip status.
|
|
* *********************************************************/
|
|
bool CMT2300A_Init(void)
|
|
{
|
|
uint8_t tmp;
|
|
|
|
CMT2300A_SoftReset();
|
|
CMT2300A_DelayMs(20);
|
|
|
|
if (!CMT2300A_GoStby())
|
|
return false; // CMT2300A not switched to standby mode!
|
|
|
|
if (!CMT2300A_IsExist())
|
|
return false; // CMT2300A not found!
|
|
|
|
tmp = CMT2300A_ReadReg(CMT2300A_CUS_MODE_STA);
|
|
tmp |= CMT2300A_MASK_CFG_RETAIN; /* Enable CFG_RETAIN */
|
|
tmp &= ~CMT2300A_MASK_RSTN_IN_EN; /* Disable RSTN_IN */
|
|
CMT2300A_WriteReg(CMT2300A_CUS_MODE_STA, tmp);
|
|
|
|
tmp = CMT2300A_ReadReg(CMT2300A_CUS_EN_CTL);
|
|
tmp |= CMT2300A_MASK_LOCKING_EN; /* Enable LOCKING_EN */
|
|
CMT2300A_WriteReg(CMT2300A_CUS_EN_CTL, tmp);
|
|
|
|
CMT2300A_EnableLfosc(false); /* Disable LFOSC */
|
|
|
|
CMT2300A_ClearInterruptFlags();
|
|
|
|
return true;
|
|
}
|
|
|
|
/*! ********************************************************
|
|
* @name CMT2300A_ConfigRegBank
|
|
* @desc Config one register bank.
|
|
* *********************************************************/
|
|
bool CMT2300A_ConfigRegBank(uint8_t base_addr, const uint8_t bank[], uint8_t len)
|
|
{
|
|
uint8_t i;
|
|
for (i = 0; i < len; i++)
|
|
CMT2300A_WriteReg(i + base_addr, bank[i]);
|
|
|
|
return true;
|
|
}
|