331 lines
8.2 KiB
C++
331 lines
8.2 KiB
C++
// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* Copyright (C) 2023-2024 Thomas Basler and others
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*/
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#include "cmt2300wrapper.h"
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#include "cmt2300a.h"
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#include "cmt2300a_params_860.h"
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#include "cmt2300a_params_900.h"
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CMT2300A::CMT2300A(uint8_t pin_sdio, uint8_t pin_clk, uint8_t pin_cs, uint8_t pin_fcs, uint32_t spi_speed)
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{
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_pin_sdio = pin_sdio;
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_pin_clk = pin_clk;
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_pin_cs = pin_cs;
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_pin_fcs = pin_fcs;
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_spi_speed = spi_speed;
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}
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bool CMT2300A::begin(void)
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{
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return _init_pins() && _init_radio();
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}
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bool CMT2300A::isChipConnected()
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{
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return CMT2300A_IsExist();
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}
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bool CMT2300A::startListening(void)
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{
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CMT2300A_GoStby();
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CMT2300A_ClearInterruptFlags();
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/* Must clear FIFO after enable SPI to read or write the FIFO */
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CMT2300A_EnableReadFifo();
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CMT2300A_ClearRxFifo();
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if (!CMT2300A_GoRx()) {
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return false;
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} else {
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return true;
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}
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}
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bool CMT2300A::stopListening(void)
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{
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CMT2300A_ClearInterruptFlags();
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return CMT2300A_GoSleep();
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}
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bool CMT2300A::available(void)
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{
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return (
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CMT2300A_MASK_PREAM_OK_FLG |
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CMT2300A_MASK_SYNC_OK_FLG |
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CMT2300A_MASK_CRC_OK_FLG |
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CMT2300A_MASK_PKT_OK_FLG
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) & CMT2300A_ReadReg(CMT2300A_CUS_INT_FLAG);
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}
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void CMT2300A::read(void* buf, uint8_t len)
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{
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// Fetch the payload
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CMT2300A_ReadFifo(static_cast<uint8_t*>(buf), len);
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CMT2300A_ClearInterruptFlags();
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}
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bool CMT2300A::write(const uint8_t* buf, uint8_t len)
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{
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CMT2300A_GoStby();
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CMT2300A_ClearInterruptFlags();
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/* Must clear FIFO after enable SPI to read or write the FIFO */
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CMT2300A_EnableWriteFifo();
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CMT2300A_ClearTxFifo();
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CMT2300A_WriteReg(CMT2300A_CUS_PKT15, len); // set Tx length
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/* The length need be smaller than 32 */
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CMT2300A_WriteFifo(buf, len);
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if (!(CMT2300A_ReadReg(CMT2300A_CUS_FIFO_FLAG) & CMT2300A_MASK_TX_FIFO_NMTY_FLG)) {
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return false;
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}
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if (!CMT2300A_GoTx()) {
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return false;
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}
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uint32_t timer = millis();
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while (!(CMT2300A_MASK_TX_DONE_FLG & CMT2300A_ReadReg(CMT2300A_CUS_INT_CLR1))) {
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if (millis() - timer > 95) {
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return false;
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}
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}
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CMT2300A_ClearInterruptFlags();
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CMT2300A_GoSleep();
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return true;
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}
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void CMT2300A::setChannel(uint8_t channel)
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{
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CMT2300A_SetFrequencyChannel(channel);
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}
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uint8_t CMT2300A::getChannel(void)
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{
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return CMT2300A_ReadReg(CMT2300A_CUS_FREQ_CHNL);
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}
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uint8_t CMT2300A::getDynamicPayloadSize(void)
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{
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uint8_t result;
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CMT2300A_ReadFifo(&result, 1); // first byte in FiFo is length
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return result;
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}
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int CMT2300A::getRssiDBm()
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{
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return CMT2300A_GetRssiDBm();
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}
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bool CMT2300A::setPALevel(int8_t level)
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{
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uint16_t Tx_dBm_word;
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switch (level) {
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// for TRx Matching Network Type: 20 dBm
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case -10:
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Tx_dBm_word = 0x0501;
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break;
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case -9:
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Tx_dBm_word = 0x0601;
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break;
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case -8:
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Tx_dBm_word = 0x0701;
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break;
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case -7:
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Tx_dBm_word = 0x0801;
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break;
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case -6:
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Tx_dBm_word = 0x0901;
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break;
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case -5:
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Tx_dBm_word = 0x0A01;
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break;
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case -4:
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Tx_dBm_word = 0x0B01;
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break;
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case -3:
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Tx_dBm_word = 0x0C01;
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break;
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case -2:
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Tx_dBm_word = 0x0D01;
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break;
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case -1:
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Tx_dBm_word = 0x0E01;
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break;
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case 0:
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Tx_dBm_word = 0x1002;
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break;
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case 1:
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Tx_dBm_word = 0x1302;
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break;
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case 2:
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Tx_dBm_word = 0x1602;
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break;
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case 3:
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Tx_dBm_word = 0x1902;
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break;
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case 4:
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Tx_dBm_word = 0x1C02;
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break;
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case 5:
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Tx_dBm_word = 0x1F03;
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break;
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case 6:
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Tx_dBm_word = 0x2403;
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break;
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case 7:
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Tx_dBm_word = 0x2804;
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break;
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case 8:
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Tx_dBm_word = 0x2D04;
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break;
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case 9:
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Tx_dBm_word = 0x3305;
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break;
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case 10:
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Tx_dBm_word = 0x3906;
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break;
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case 11:
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Tx_dBm_word = 0x4107;
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break;
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case 12:
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Tx_dBm_word = 0x4908;
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break;
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case 13:
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Tx_dBm_word = 0x5309;
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break;
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case 14:
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Tx_dBm_word = 0x5E0B;
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break;
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case 15:
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Tx_dBm_word = 0x6C0C;
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break;
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case 16:
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Tx_dBm_word = 0x7D0C;
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break;
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// the following values require the double bit:
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case 17:
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Tx_dBm_word = 0x4A0C;
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break;
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case 18:
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Tx_dBm_word = 0x580F;
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break;
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case 19:
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Tx_dBm_word = 0x6B12;
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break;
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case 20:
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Tx_dBm_word = 0x8A18;
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break;
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default:
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return false;
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}
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if (level > 16) { // set bit for double Tx value
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CMT2300A_WriteReg(CMT2300A_CUS_CMT4, CMT2300A_ReadReg(CMT2300A_CUS_CMT4) | 0x01); // set bit0
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} else {
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CMT2300A_WriteReg(CMT2300A_CUS_CMT4, CMT2300A_ReadReg(CMT2300A_CUS_CMT4) & 0xFE); // reset bit0
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}
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CMT2300A_WriteReg(CMT2300A_CUS_TX8, Tx_dBm_word >> 8);
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CMT2300A_WriteReg(CMT2300A_CUS_TX9, Tx_dBm_word & 0xFF);
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return true;
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}
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bool CMT2300A::rxFifoAvailable()
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{
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return (
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CMT2300A_MASK_PKT_OK_FLG
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) & CMT2300A_ReadReg(CMT2300A_CUS_INT_FLAG);
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}
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uint32_t CMT2300A::getBaseFrequency() const
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{
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return getBaseFrequency(_frequencyBand);
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}
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FrequencyBand_t CMT2300A::getFrequencyBand() const
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{
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return _frequencyBand;
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}
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void CMT2300A::setFrequencyBand(const FrequencyBand_t mode)
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{
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_frequencyBand = mode;
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_init_radio();
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}
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void CMT2300A::flush_rx(void)
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{
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CMT2300A_ClearRxFifo();
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}
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bool CMT2300A::_init_pins()
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{
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CMT2300A_InitSpi(_pin_sdio, _pin_clk, _pin_cs, _pin_fcs, _spi_speed);
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return true; // assuming pins are connected properly
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}
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bool CMT2300A::_init_radio()
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{
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if (!CMT2300A_Init()) {
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return false;
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}
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/* config registers */
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switch (_frequencyBand) {
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case FrequencyBand_t::BAND_900:
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CMT2300A_ConfigRegBank(CMT2300A_CMT_BANK_ADDR, g_cmt2300aCmtBank_900, CMT2300A_CMT_BANK_SIZE);
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CMT2300A_ConfigRegBank(CMT2300A_SYSTEM_BANK_ADDR, g_cmt2300aSystemBank_900, CMT2300A_SYSTEM_BANK_SIZE);
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CMT2300A_ConfigRegBank(CMT2300A_FREQUENCY_BANK_ADDR, g_cmt2300aFrequencyBank_900, CMT2300A_FREQUENCY_BANK_SIZE);
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CMT2300A_ConfigRegBank(CMT2300A_DATA_RATE_BANK_ADDR, g_cmt2300aDataRateBank_900, CMT2300A_DATA_RATE_BANK_SIZE);
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CMT2300A_ConfigRegBank(CMT2300A_BASEBAND_BANK_ADDR, g_cmt2300aBasebandBank_900, CMT2300A_BASEBAND_BANK_SIZE);
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CMT2300A_ConfigRegBank(CMT2300A_TX_BANK_ADDR, g_cmt2300aTxBank_900, CMT2300A_TX_BANK_SIZE);
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break;
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default:
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CMT2300A_ConfigRegBank(CMT2300A_CMT_BANK_ADDR, g_cmt2300aCmtBank_860, CMT2300A_CMT_BANK_SIZE);
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CMT2300A_ConfigRegBank(CMT2300A_SYSTEM_BANK_ADDR, g_cmt2300aSystemBank_860, CMT2300A_SYSTEM_BANK_SIZE);
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CMT2300A_ConfigRegBank(CMT2300A_FREQUENCY_BANK_ADDR, g_cmt2300aFrequencyBank_860, CMT2300A_FREQUENCY_BANK_SIZE);
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CMT2300A_ConfigRegBank(CMT2300A_DATA_RATE_BANK_ADDR, g_cmt2300aDataRateBank_860, CMT2300A_DATA_RATE_BANK_SIZE);
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CMT2300A_ConfigRegBank(CMT2300A_BASEBAND_BANK_ADDR, g_cmt2300aBasebandBank_860, CMT2300A_BASEBAND_BANK_SIZE);
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CMT2300A_ConfigRegBank(CMT2300A_TX_BANK_ADDR, g_cmt2300aTxBank_860, CMT2300A_TX_BANK_SIZE);
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break;
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}
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// xosc_aac_code[2:0] = 2
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uint8_t tmp;
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tmp = (~0x07) & CMT2300A_ReadReg(CMT2300A_CUS_CMT10);
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CMT2300A_WriteReg(CMT2300A_CUS_CMT10, tmp | 0x02);
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/* Config GPIOs */
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CMT2300A_ConfigGpio(
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CMT2300A_GPIO2_SEL_INT1 | CMT2300A_GPIO3_SEL_INT2);
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/* Config interrupt */
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CMT2300A_ConfigInterrupt(
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CMT2300A_INT_SEL_TX_DONE, /* Config INT1 */
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CMT2300A_INT_SEL_PKT_OK /* Config INT2 */
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);
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/* Enable interrupt */
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CMT2300A_EnableInterrupt(
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CMT2300A_MASK_TX_DONE_EN | CMT2300A_MASK_PREAM_OK_EN | CMT2300A_MASK_SYNC_OK_EN | CMT2300A_MASK_CRC_OK_EN | CMT2300A_MASK_PKT_DONE_EN);
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CMT2300A_SetFrequencyStep(FH_OFFSET); // set FH_OFFSET (frequency = base freq + 2.5kHz*FH_OFFSET*FH_CHANNEL)
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/* Use a single 64-byte FIFO for either Tx or Rx */
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CMT2300A_EnableFifoMerge(true);
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/* Go to sleep for configuration to take effect */
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if (!CMT2300A_GoSleep()) {
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return false; // CMT2300A not switched to sleep mode!
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}
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return true;
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}
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